The Digital Of Closed-loop Multi-channel Conversion Test

The digital measurement tester is telemetry system supporting system, it is an importantand indispensable part of aircraft launch teat, ballistic flight test and other aircraft testexperiment. It is used to get the analysis of the performance of the system being tested inflight test status parameters and flight data environment, to consider the performance of thetested system, stability or system failure analysis, in order to provide related technology anddata security. Due to the rapid development of digital technology, the digital transformationmeasurement tester is used as remote testing system and it is used more widely for itsadvantages of stability, efficiency, accuracy and convenient debugging. Based on theunderstanding of the research status and development trend of digital conversion devicedomestic and overseas, on the analysis of digital transformation tester function index, theauthor puts forward the design of closed loop multi-channel digital transformation test device,this system adopts embedded design method, it uses computer simulating upper computer totransmit signal, the hardware circuit of single chip processor main controller chooses FPGAchip. FPGA can realize the combination and sequence logic, it can be more parallel execute tocommand module. The interior of it has rich resources of the trigger. The design of FPGA issimple for design, low cost for development and low consumption for power, etc, especiallyits rich I/O port resources, and it provides the possibility of implementation for the digitaltransformation function integration.The achievements of this paper are: based on the hardware Ethernet protocol chipW5500and the design of FPGA, we implement a set of real-time communication with PCdata acquisition test system, which can realize high-speed data acquisition and real-time datatransmission of signals. The digital transformation test device can set the form of eitherchannel signal in the form of (instruction pulse frequency, pulse number) There is no mutualinterference between different channel signals, so the tester can possess informationefficiently and rapidly. For itself, it can be self-checking alone, used to detect whether signalsource can send right number, whether it can you test data back, and whether the power supply is normal. It provides a convenient way for timely eliminating the test result errorcaused by the error tester. Relying on FPGA and the Ethernet protocol chip W5500high SPC,making the TCP/IP as communication protocol, system reasonable layout to achieve reliable,high automation, integration to complete each signal sending and displaying back reading andstable communication with the upper machine simultaneously, the function of the softwareand test process visualization. The digital transformation test device integrates the function oftraditional digital transformation tester and instruction to transforming the function of thetester, generated by FPGA to realize the command signal (service signals, imp pulse,instructions, etc) and by accepting, back reading the feedback of signal to verify the digitalmeasurement tester issued the correctness of the digital simulation signal source, achieved bythe output signal corresponding analyze and accept feedback signal analyze to detect theintegrity of the performance parameters of the function.