The Implementation Of Multi-channel And High-resolution TDC Circuit

Precise time-interval measurement technology is widely applied to deep spacecommunications, electric power transmission, aerospace, navigation and positioning,large-scale physics experiments, etc. Especially in high-energy physics experiments,the use of flight time differential for particle identification efficiency is directlyrelated to the resolution of time-interval measurement.Time-to-digital converter circuit is the core module in precision time-intervalmeasurement. The design of FPGA-based TDC can effectively shorten developmentcycle, greatly reducing system size, lower cost, improve the flexibility and reliabilityof design, and there is no tape out risk, possessing great value for research anddevelopment.This paper studies how to use dedicated carry resources of adders inFPGA to implement high-precision time-digital converter circuit.The thesis analyzes the FPGA-based Wave Union TDC in detail. Wave UnionTDC is based on the idea of combining "coarse" time counter and "fine" timemeasurement, cascade adders into carry chain, utilize its intrinsic carry delay toimplement time interpolation for the hit signal. A wave union launcher creates a"wave union" with several0-to-1or1-to-0logic transitions for each input hit and feedthe wave union into the TDC delay chain/register structure, making multiplemeasurements, effectively sub-divide "ultra-wide bins" caused by the FPGA logicarray block (LAB) structure and improves measurement precision, thus implement the"fine timing measurements". Meanwhile ordinary binary counter is used to implement"coarse counting". Wave Union TDC has advantages of a low cost, easy to implementand flexibility, moreover it has been implemented20ps RMS resolution already,which is a high-precision time of digitizing measurement scheme.The main work of the issue is using the Wave Union TDC to set up read-outelectronics system. The hardware circuit is mainly constituted by front-end signalinput module, TDC module implemented in the FPGA, the data read-out module,clock module, and the power management module, using Mentor EE2005software tocomplete the circuit schematic and PCB design. Considerations of signal integrity andpower integrity are also taken to our design. The FPGA logic design of data read-outincludes the reception, preprocessing, caching of TDC data, and the communicationbetween it and VME bus controller, this part is implemented by the use ofcomprehensive FPGA development software Quartus II12.0and HDL language simulation software ModelSim-Altera6.5with Verilog HDL.The scheme of VME bus data read-out is adopted in the design. Test results showthat the linearity degree of this TDC system is fine, while the RMS resolution oftime-interval measurement is better than35ps,basiclly fulfills standard of design.