Research And Design Of DPWM Module Applied In Digital Dc-Dc Converter

With the development of the Internet of Things,people are increasingly demanding the portability and endurance of electronic products.Switch mode power supply(SMPS)has the advantages of small size,light weight,high efficiency,stable performance and so on,and has been widely used in various fields such as aerospace,communications,computers,electronics and so on.The core of the switching power supply is the switching converter,which includes the power circuit and the control circuit.However,the stability of the traditional analog switching power supply control circuit is poor,and it is easily affected by the process,voltage,and temperature.Therefore,the DC-DC converter based on digital control People's attention.This article studies the basic structure of digital DC-DC and its digital pulse width modulation(Digital Pulse Width Modulation,DPWM)module,analyzes and compares several different DPWM control module schemes,and proposes two FPGA-based internal carry The chain unit structure of the mixed DPWM circuit structure is:phase-locked loop(Phase Locked Loop,PLL)and carry chain mixed two-stage synchronous trigger DPWM circuit,mixed mode clock manager(Mixed Mode Clock Manager,MMCM)and carry chain Double edge trigger DPWM circuit with mixed structure.The two circuits mainly use a mixed structure of counter,comparator,fixed phase shift phase locked loop unit and high speed carry chain,which effectively improves the resolution.The proposed design does not require manual wiring or placement,consumes very little hardware resources,and does not rely on specialized phase-locked loops or clock management resources.The two control circuits proposed in this paper are implemented on the programmable gate array devices of Altera and Xilinx development board resources,respectively.The experimental results of the mixed two-stage synchronous trigger DPWM circuit of PLL and carry chain on the Altera development board show that when the input reference clock operating frequency is 70MHz,the resolution of the structure can reach 56ps,and the circuit also has a wider switching frequency The adjustment range is 1.85%-98.51%and the better linearity R~2 is 0.9932.The dual-edge triggered mixed structure DPWM circuit implemented by MMCM and carry chain on the Xilinx development board shows that when the input reference clock operating frequency is110MHz,the resolution of the structure can reach 36ps,and the switching frequency adjustment range is 2.56%-97.28%,And the proposed circuit meets the expected design.