| In the clinical positron emission tomography imaging PET examining technique of nuclear medicine, time information measurement is an important factor in image reconstruction of imaging devices. In fixed targets and collision experiments of high-energy physics, time measurement has become an important means of identifying particles. Therefore, there is much point in the research of precise time measurement in modern science and technology. TDC, short of time-to-digital conversion, is a basic method of measuring time. TDC, based on FPGA, has become hot due to its flexibility and high speed and low cost in the current time measurement techniques.The main task of this thesis is to design a highly precise TDC system based on FPGA. Firstly, the thesis discusses three fundamental issues: the law of achieving addition carry chain cascade in FPGA, the coherence of tapping delay and sampling clock. It also designs and verifies the logic structure of addition carry chains. Secondly, in the course of whole design, it is guaranteed that the layout and wiring are not influenced by other modules through logic lock and incremental compilation. After the timing simulation of the design, it is discovered that there is a long inherent wiring delay of the sampling signal in carry delay chain, thus wasting some delay units. Directed at this problem, the thesis adopts the two methods of shortening the delay of sampling time and adding delay of testing signals to optimize the wiring, with the benefit of obvious performance improvement. In the end, the optimized TDC is tested in the Cyclone II chip EP2C35F672C6. It turns out that usage of resources is3%, measurement resolution is less than60ps,precision is less than50ps and linearity is good (-0.84LSB≤DNL≤0.78LSB,-1.16LSB≤INL≤0.88LSB).After test and verification, TDC based on the time interpolation in FPGA has the features of low cost, high resolution and high precision, making it very promising in the multi-channel TDC designs. |
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