Hardware Design And Debugging Of Data Acquisition And Pre-processing System Of The Vector Array Positioning System

This thesis is based on a vector array sonar system, the vector array sonar system basedon the passive principle, making use of the noise generated target navigation to detect thetarget. The vector array sonar system mainly consists seven parts of vector hydrophone array,signal conditioning, data acquisition and pre-processing system, high-speed data transmissioncontrol systems, data storage systems, data processing systems and the PC. This thesisdiscusses the main content of the hardware design and debugging of data acquisition andpre-processing system of the vector array sonar system.Data acquisition and pre-processing system to complete the two features: first a multipletarget signal acquisition; second front-end preprocessing data collected. The system uses thesampling circuit with8ADS1178sampling chips to achieve64-way signal acquisition of thetarget, the sampling circuit in the FPGA control and sampling data obtained in the FPGApackage cache. Due to the impact of the manufacturing process differences, each vectorhydrophone channels have different signal sensitivity for different frequencies signals, andbetween the respective channels, the orthogonal deviation is not the same for differentfrequencies signals. So to the data collected at different frequencies, we must makecorrespondingly the sensitivity and the orthogonal compensation. Before compensating, weshuold complete firstly the data in the time domain to the frequency domain transformtion.For the collected data, in the FPGA, the system implements the FFT processing to completethe data from the time domain to the frequency domain transformtion.Firstly, this paper elaborates the data acquisition and pre-processing system hardwarecircuit design thinking, and introduces specificly the sampling circuit, FPGA configurationfunction circuit, ethernet circuit, power supply circuit as well as CPCI interface circuit design;then elaborates the AD sampling module as well as the sampling data pre-processing moduledesign ideas, and describes specificly implementations of AD sampling module, as well as thedata writing control module, the ping pong buffer module, the data read-out control moduleand the data FFT processing module of the pre-processing module; finally, throughappropriate circuit debugging and analysis of data simulation processing results, verifying thatthe system can complete correctly the data acquisition and pre-processing functions.