The Research And FPGA Implementation Of Demodulation Technology Of Digital Communication Signals

The operating frequency band of modern communication system increases the more, so that data volume and speed requirement of signal processing enhances unceasingly. As the key technology of communication, modulation-demodulation, involving a large number of complex mathmatical operations and requiring high-speed data processing capability, is obviously no exception. Traditional DSP chip is increasingly difficult to meet the hardware needs of modern modulation-demodulation technology because of its inherent characteristics of serial processing. FPGA device is a big attraction in high-speed applications beacause it is reprogrammable, and owes a strong parallel processing ability and high integration, and has a complete development platform, and the improving cost performance also promotes large volume FPGA applications in various fields. The best solution for wide-scope intermediate frequency sampling software radio, that is common structure in the field of communication, takes exactly FPGA as the core of hardware in the IF. Therefore, the research of FPGA implementation of digital modulated signals’demodulation technology has a wide application prospects.Proceed from the basic modulation mode of communication signal, guided by the ideas and architecture of software radio, this paper successfully designed a demodulator group based on FPGA, including four non-coherent demodulators of2ASK,2FSK, BPSK, QDPSK signal and a coherent demodulator of QPSK signal. The mathematical algorithms and time-domain measurement methods are both researched in non-coherent demodulation scheme, focusing on the FPGA implementation points and anti-noise performance of the former. Close-loop carrier synchronization and close-loop symbol synchronization based on PLL theory are elaborated in coherent demodulation scheme. Combining CPAFC frequency locking algorithm with Costas phase locking loop, the capture range of carrier frequency offset can be improved obviously. Using Gardner algorithm and digital interpolation, symbol synchronization module has good convenience for FPGA implementation, and excellent synchronizing performance as well.Through improving and optimizing for FPGA scheme by Matlab performance simulation and comparison of demodulation algorithms, hardware implementation complexity of demodulators can be reduced under a enough premise of anti-noise performance. All demodulators are described using Verilog HDL on Quartus Ⅱ9.1platform, and the function verification of FPGA design is proceeded on the simulation software of Modelsim. The results show that these demodulators in this paper can demodulate the modulating signal with high speed and real time, the maximum operating frequency is more than170MHz, which is tested on low-cost CycloneⅢ series FPGA device of Altera company. Moreover, each demodulator has good noise immunity whose bit error rate is lower when the S/N is in the range of lOdB to positive infinity. It means that these demodulators can be directly applied to practical engineering.For the hardware test part of demodulator, this paper put the laboratory’s existing FPGA development board to use, through designing the data interface between demodulator group and A/D chip and ethernet chip, a FPGA-centered demodulation test platform was built successfully. This platform has the following two test methods. Transmitting demodulation results to PC, the average BER performance in the period of time was tested. Using SignalTap Ⅱ analysis tool, the current working conditions of internal signals can be detected directly. The final hardware test results show that the FPGA implementation scheme of each demodulator in this paper is effective and feasible.