Research On The Resource Optimization In The Logic Design Of SVD Algorithm

3-D fluorescence analysis technology is a new effective way for analysis ofcomplex systems. It has wide application prospects in life science, material science,environment science and so on.3-D fluorescence analysis algorithm is based onlarge-scale matrix operations and has high complexity. So it is very hard forpopularization and application in embedded devices. The programmable logic deviceFPGA has high parallelism and high speed, can solve the calculated requirements of3-D fluorescence analysis algorithm well in the embedded environment, but the hugecomputation of3-D fluorescence analysis algorithm leads to the big demand ofFPGA resources. Consider that3-D fluorescence analysis don’t have real timerequirement, how to reduce the consumption of hardware resources in logical designof3-D fluorescence analysis algorithm is studied in this paper.Singular value decomposition (SVD) is the computing-intensive and the mostcritical component of the3-D fluorescence analysis. Its hardware resourcesutilization in the logical design directly influences the hardware resources demandof3-D fluorescence analysis. In order to reduce the consumption of hardwareresources of the SVD processor, the CORDIC-based angle calculation structure andthe CORDIC-based two-side rotation structure in the SVD processor are improvedwith “functional modules reuse” and “parallel to serial conversion” strategies inlogic design. The following is the contents of this work.First, with the use of “functional modules reuse” strategy, the angle calculationstructure is improved to increase the resources utilization rate. The improvedstructure removes two outside shifters and saves resources through reusing theinternal shifter of CORDIC.Then, two improved schemes are presented, and the parallel two-side rotationstructrue and the serial two-side rotation structrue are designed accordingly to getrid of the free resources caused by the data dependence between the left rotation andthe right rotation in the two-side rotation. The parallel two-side rotation structruerelieves the data dependence and relizes the parallel computation of them. It reducescertain area as well as the processing time. The serial two-side rotation structrueremoves two CORDIC modules by reusing the other two CORDIC modules, andsaves a lot of resources Consider that the bit-serial structure has advantages on the hardware resourceand the clock frequency than the bit-parallel structure, with the use of “parallel toserial conversion” strategy, the bit-serial optimizations for the improved anglecalculation structure, the parallel two-side rotation structrue and the serial two-siderotation structrue are made by using the bit-serial CORDIC, bit-serial adder orsubtractor, and bit-serial shifter. And the optimizations can reduce a lot of hardwareresources futher.Finally, the correctness and the optimization effect of the optimized structuresare verified. To verify the correctness, the Verilog HDL is used to describe theimproved structures. And then, the improved structures are simulated on ModelSimby writing the testbenches. To verify the optimization effect, the original structuresare realized with the equivalent function and in the same conditions, and theirperformance comparison shows: when the data is the32bits wide, the improvedangle calculation structrue saves17.01%resources, the parallel two-side rotationstructrue saves38.19%resources and the serial two-side rotation structrue saves43.59%resources.