Design Of The High Efficiency Bit Line Driver In The Flash

In recent years, with the rapid development of the digital processor technology, flash memory has been widely used in mobile phones, digital cameras, multimedia players and other electronic products. With the advantage of its small size, low electromagnetic interference (EMI) and low-cost, charge pump has become the main way to produce the required high voltage when flash memory is programming and erasing. As portable products becoming more and more popular, minimizing power consumption is a key issue, as a result, small ripple and high efficiency are two challenges in the design of charge pump especially while it acts as on-chip power supply of modern sub-micron IC.Based on the practical application requirements of NOR FLASH, a wide input wide output range, low ripple, low overshoot and high efficiency bit line driver has been designed. The main work and innovations include:1. A variety of high voltage generating circuit, charge pump structure and its regulator system has been introduced systematically. By the discussing and comparison of various architectures of the charge pump circuit, the cross-coupled structure is adopted in this design and a system solution for the bit line driver is proposed according to the system specification.2. For a wide input range (1.5V～2.1V), an adaptive gain control technique which consists of6X,5X and4X three gain modes is adopted to achieve a low ripple, low overshoot and high efficiency charge pump circuit design. Moreover, the gain mode can achieve a different gain of1X to NX (N is an integer) according to the different applications.3. For a wide output range (0.1mA～1.6mA), a light load current detection circuit is designed to detect the output load, according to which the light load modulation is used to reduce overshoot、ripple and improve efficiency under light load conditions. 4. In the feedback control aspect, a novel variable frequency modulation combined with current modulation is developed to regulate output voltage to a constant voltage6.75V, which achieves high efficiency as well as low output voltage ripple.The entire system including the main circuits and the sub circuits is simulated and designed in MXIC75nm1P3M CMOS process using Spectre of Cadence. The simulation results show that the expect goals have been achieved besides the chip area.