Study On Key Techniques Of CMOS Satellite Navigation Receiver Integrated Chip

In this thesis, the design technology of some key blocks for CMOS navigationsatellite receiver is analyzed, focused mainly on the RF front-end architecture, and thebasic theory of filter and phase locked loops. Then put forward specific solutions to thefilter and VCO to meet the technical characteristics of the receiver.First, An active band-pass filter with variable pass-band width is designed forlow-IF receiver. The filter which adopts Active-RC architecture is a fourth-orderButterworth-type band-pass filter. It can be switched to three different frequencybandwidth to satisfy the low-IF receiver channel selectivity. The current of the maincircuit is only1.2mA, fully meet the requirements of the satellite navigation receiver forlow power.This proposed LC VCO has been fabricated in TSMC commercial0.18um RFCMOS process. Using a combination of switched binary-weighted MIM capacitor arrayand MOS variactors. This VCO achieves a tuning range of2.69GHz~3.30GHz and agood performance in phase noise.