Key Technologies Research On Satellite Navigation Receiver Anti-jamming RF Chip

The Global Navigation Satellite Systems(GNSS)are widely applied in aviation,aerospace,navigation,military and consumer electronics etc.,which recently seen significant development worldwide.However,the problem that the signal of satellite navigation is so weak that it is vulnerable to unintentional or intentional electromagnetic interference also urgently needs to be addressed.As the critical components in the satellite navigation receiver,the radio frequency(RF)front-end circuit decides the anti-jamming function and performance.The satellite navigation receiver faces the development trend of lightweight,mini-type and low power consuming.Therefore,it is useful of the research on highly integrated anti-jamming RF chip of satellite navigation receiver.According to the demands of anti-jamming satellite navigation receiver chip,the key technologies are studied in this dissertation,such as configurable low noise amplifier,configurable image rejection mixer and active polyphase filter,configurable intermediate frequency filter,precise decibel linear programmable gain amplifier and digital automatic gain control.Based on the research,a demo-chip is designed,fabricated and tested.The main content of this dissertation is summarized as follows.Firstly,the low IF architecture is researched and selected for anti-jamming RF chip.A dual-channel anti-jamming RF chip architecture are presented.The multi-work-mode and multi-frequency-point design is proposed to meet requirements for compatibility and low power consuming.Then,two methods are studied and proposed,one is the performance parameter calculation method suitable for receiver chip,another is the parameter decomposition method for module design.Secondly,The proposed fully differential configurable LNA is based on the cross-coupled common gate topology to achieve wideband input matching and low noise figure.The bias current of the LNA is digitally adjustable by varying gate bias voltage for different anti-jamming work modes.This allows simultaneous trading of power with both gain,noise and linearity.For different work modes,the post simulation results show that the LNA can work at 1.2 and 1.5GHz,the noise figure(NF)is 2.5~8.1dB,the gain is 13~22dB,the input third intercept point is 0~6dBm,the current consumption is 1~7mAThirdly,the image rejection problem is studied.A novel active reconfigurable mixer is proposed,which is based on the traditional active mixer and current-driven passive mixers.The mixer is adjustable by control bits,in order to trade power with both gain,noise and linearity.The measurement results show that the configurable mixer can work at 1.2GHz and 1.5GHz,the NF is 13~22.5d B,the gain achieves 7.5~16d B,the IIP3 is-3.5~22dBm,the current consumption is 2.4~8.4mA for different anti-jamming work modes.And then,a passive poly-phase filter(PPH)and a active poly-phase filter are adopted to reject the image signal for different work modes.A novel circuit architecture for active polyphase filter is proposed and analyzed.Compared to other conventional active polyphase filters,the proposed polyphase filter uses a simpler structure to achieve strong image rejection in a wide band while obtaining lower power consumption,higher operating frequency and smaller chip area.From the measurements,the active polyphase filter shows an image rejection ratio of 48.5dB at frequencies of 5.5MHz to 26.5MHz,a voltage gain of 6.8d B and an IIP3 of 3.8d Bm at 16 MHz while consuming only 3.1mA from a 1.8-V supply.Fourthly,this paper presents a novel adjustable linearity and power consumption Gm-C band-pass filter(BPF)for different anti-jamming work modes with reconfigurable transfer function and selectable bandwidth for different navigation frequency point.The BPF with 20 MHz bandwidth is implemented as a low-pass filter(LPF)in series with a high-pass filter(HPF).The BPF with 4MHz bandwidth is implemented as a single BPF structure.In order to maintain the desired linearity at the minimum possible power dissipation,an operational transconductance amplifier(Gm)is proposed to provide three modes of operation switched for handling interferences of different magnitude.From the measurements,in different work mode,the filter achieves IIP3 of-4~25dBm/-3~27dBm dBm(4/20MHz)while consuming 9.6~148/15~168mW(4/20MHz),respectively.A novel circuit architecture for programmable gain amplifier(PGA)is proposed,which includes a coarse gain control block employing an R-2R resistor ladder attenuator and a Binary-Weighted dB-linear fine gain control block and achieves wide precise digital decibel-linear gain control.From the measurements,the PGA shows a decibel-linear gain range of 48 d B with a gain error of less than 0.18 dB,a gain step of 0.86 d B.Finally,based on the research above,a fully integrated RF front-end demo-chip is designed,fabricated in TSMC 180 nm CMOS technology.The measurement results validate the correctness and effectivity of the research work in this dissertation.