The Design And Reliability Analysis Of Pop

Package on Package (POP), a typical type of3D package solutions, which could integrate memory and logic dies together, has become the most important part of handheld device market seeking for thinner and smaller outline. Compared with die stacking, the advantage of stacking packages is that packages can be fully tested good prior to stacking to achieve stable stacking yield. Besides, in the POP, the selection of device combination is more flexible and so it has become priority selection for3G mobile phone and digital camera and is widely used in the smart phones and Personal Digital Assistant (PDA) devices. However, due to the complex structure of POP, the heat dissipation problem, warpage control caused by coefficient of thermal expansion (CTE) mismatch of package materials and drop reliability have become the bottlenecks of POP’s further development. Hence the study of POP reliability is critical for the development of POP.In this study, the thermal analysis of an actual POP device under its working state was performed by considering the natural thermal convection on the POP device’s outer surfaces based on finite element method. The computational results were verified by designed experiments. Through the method, the relationships between die power and the difference value of maximum temperature between the top package and bottom package was studied and the strategy for POP thermal management was proposed. Besides, considering the Printed Circuit Board (PCB) and bottom substrate as the main path of POP’s dissipation, the parametric study was carried out and the result showed that the thermal conductivity increase of PCB and bottom substrate below the threshold could reduce the maximum temperature in the POP effectively.The effect of top package’s initial warpage and die power in two stacked POP on the warpage and stress after reflow and under working state was studied by birth and death elements and thermal stress analysis method. The maximum von Mises of solder ball array was small when the initial top package was flat and the location of the maximum von Mises was on the solder ball array between PCB and the bottom package. Besides, the maximum von Mises of solder ball array under working state was small when the top package’s initial warpage was between-20μm and20μm.The warpage and stress under working state was decreased with the increase of die power and the effect on bottom package’s warpage was more obvious.PCB board has been designed according to JEDEC standard of drop test.1500G, 0.5ms, half sine pulse was selected as the drop test condition. Except static electrical test, transient signal during the drop was detected by high speed acquisition device. The result showed that the failure location was on the bottom package in the two stacked POP and three stacked POP and two failure patterns were observed by failure analysis. Besides, the SAC125sphere alloy offered better drop performance than the SAC305alloy.