Research About Current-mode LNA And Mixer Of UWB RF Receiver

With the rapid development of wireless communication technology, the design ofRF front-end circuit with low voltage low power consumption has become more andmore important. Currently, the conventional voltage-mode circuit is mostly adopted,but the circuit with low voltage and low power consumption design is so complexbecause there are too much high impedance nodes in it. By contrast, current-modecircuit which uses current as signal variables can get better performance. Recent years,the papers about current-mode technology are mostly related of narrow band, however,the UWB which grows up after the period of1990s with high data speed and lowpower consumption has huge development potential, therefore, this paper applycurrent-mode technology to the design of UWB circuit.This paper proposed three current-mode UWB front-end circuits, the mainachievements of this work consist of following aspects:(1)A CMOS current-mode differential LNA working at3-5GHz is presented. Thedifferential common-gate CMOS transistors are introduced as the input stage, thedrain current is directly amplified by current mirror. Capacitance cross couplingtechnology is adopted on purpose of noise reduction. The power consumption of theLNA is only12.4mW with supply voltage1.2V, the minimum noise figure is1.78dB,gain is15.9dB and S11is less than-11dB.(2)Another lower complexity lower voltage current-mode3-5GHz LNA is alsopresented in this paper. The differential common-gate CMOS transistors encircled byan integrated transformer are introduced as the input stage on purpose of noisereduction. A common-source amplifier as the second stage achieves high gain andsupply current to the mixer. The power consumption is11mW with a0.8-V supplyvoltage. This proposed LNA achieves the maximum power gain (S21) of19.1dB withthe3-dB band from3to5GHz and input reflection coefficient (S11) of less than–9dB from3to5GHz. The minimum noise figure is2.59dB.(3) A3-5GHz current-mode Mixer is proposed. The current RF signal directlyflows to the switch level. The shunt-peaking technology is also adopted. The powerdissipation is8.2mW with a1.2-V supply voltage, the maximum power conversiongain of6.9dB, the maximum double side band noise figure is6.2dB, and IIP3is-1dBm at4GHz. The proposed circuits are simulated by ADS2008. The pre-layout simulationresults show that they are more excellent than recently published CMOS designs.