The High-speed Linear Ccd Scanning Image Acquisition And Storage System Design

In this paper, a high-speed image acquisition and storage system is designed according to the system requirements. The linear array IL-P3-512CCD is used as the photo detector and a series of timing drivers are designed with VHDL language and simulated in Quartus II software. After the process of filtering and noise reduction, the output voltage signals are sent to the analog-to-digital chip. A data buffer FIFO is designed in FPGA to be the interface between A/D and DSP devices. The digital signals stored in the FIFO are read to the DARAM in the DSP, and then saved to the SD card in the file system of FAT32. Tests are used to verify the performance of the designed system, compare the reconstruction of the data in the SD card between the output signal of the CCD, and the result shows the design of the image acquisition and storage system is feasible when the FPGA and DSP are used.The solution using FPGA and DSP in this paper is more suitable for a high-speed CCD data acquisition and storage system design, owing to the flexibility of the FPGA and the excellent mathematical operation ability of the DSP device.