Design And Implementation Of Shared-Memory Circuit For GPON ONU

With the development of Internet application, video application and high-definition television, present bandwidth becomes insufficient for the demand, and the access network faces an even greater challenge. As a representative of the broadband access technologies, FTTx is an effect way to break the bottleneck of access and becomes the ultimate form of "last mile" in the future. As the most potential fiber access technology, GPON (Gigabit-Capable Passive Optical Network) is wide bandwidth, high-speed and abundant user ports etc. With the performance improvement and cost reduction of optical devices, GPON’s advantage in the access network will become more apparent.Data exchange memory structure is the key to the GPON system. Shared-memory is a mature, common structure of data exchange. This dissertation focuses on hardware design of the shared-memory circuit for GPON ONU.The dissertation introduces the development of passive optical network, contrast several existing PON techniques, describes the state and advantage of GPON, and analyzes the influence of shared-memory for GPON system. The dissertation also describes GPON global structure, work principles, GEM encapsulation and design structure.GPON ONU needs to use the data memory circuit for flow control and bandwidth allocation because both downstream and upstream data transmission may appear congestion. According to the flow diagram of shared-memory structure, the dissertation gives the design and implementation of the shared-memory circuit for GPON ONU. Based on the analysis of uplink and downlink data flow, the dissertation puts forward a detail design scheme for shared-memory circuit including overall structure, module partitioning and design and implementation of each module. The shared-memory circuit includes modules such as ethernet gemac, IBS, IDQ, QP, ODQ_SCH, MCL, OBS, MPI, FIFO and CRC, and RTL design of each module is completed with Verilog HDLFinally the dissertation describes the functional simulation and FPGA prototyping verification for the RTL design of the main module and the whole shared-memory circuit. The results of functional simulation FPGA prototyping show that the design of the ONU shared-memory circuit can meet the design requirements in function and performance.