Sampling System Based On1-bit And Conventional Compressive Sensing

The digital signal acquisition from analog signal plays an important role in digitalsignal processing system. Conventional signal acquisition systems sample a signal at arate of at least two times its bandwidth for the perfect signal reconstruction, and thencompress the sampled data for storage and transmission. The compressive sensing (CS)theory gives rise to a new solution to signal acquisition and reconstruction. It supportssensing directly the compressed data by random measure at extremely low rate, and thussignificantly saves the system resource. The perfect signal reconstruction form linearmeasurement is guaranteed with extremely high probability by the CS theory.The CS indicates that if we want to get a perfect reconstruction, we need moremeasurements and accurate quantization，we know that it is very hard for the hardware.However, to date, the CS theory has assumed primarily real-valued measurements; TheCS reconstruction has been shown to be robust to multi-level quantization of themeasurements, in which the reconstruction algorithm is modified to recover a sparsesignal consistent to the quantization measurements. Both the real-valued method and themulti-level quantization method, we need to store and transmit more data. The recentlyproposed1-bit CS has been demonstrated that accurate and stable signal acquisition isstill possible even when each measurement is quantized to just a single bit. Thisproperty enables the design of simplified CS acquisition hardware based around asimple sign comparator rather than a more complex analog-to-digital converter (ADC).However, the reconstruction signal usually gets40dB even when the number of themeasurements is three times of its length.In this thesis, we proposed a new sampling system based on1-bit CS andconventional CS. This sampling system combines the CS with1-bit CS, formingparallel sampling system. In this system, the1-bit CS channel can increase the priorinformation of the signal, and the prior information is obtained online. The samplingsystem has advantage of both the CS and1-bit CS. In this thesis, we combine the twoconstrains of the CS and1-bit CS, so we can get high-rate and high-accuratereconstruction signal by this sampling system even when the sampled signal is low-rateand low-accurate, which is cannot realize in ADC or AIC system. We prove the systemcan be solved by Restricted–Step Shrinkage algorithm which is effectively used to solve1-bit CS model. In this thesis, we not only give the idea and theory analysis of the sampling system but also show the implementation structure of the system. Finally thesimulations show that this system performs better than the conventional CS system and1-bit CS system.