Research For Extensible, Cycle-accurate And Fast Multi-core Simulators

To design novel computer architectures, researchers have to iteratively refine and evaluate the design alternatives. Due to the poor flexibility and high cost in both time and economy to produce new hardware, researchers generally use software simulators for architecture research and design. As a result, full-system simulators are extremely useful in evaluating design alternatives for multicore.However, state-of-the-art multicore simulators either lack good extensibility due to their tightly-coupled design between functional model (FM) and timing model (TM), or cannot guarantee cycle-accuracy. This paper conducts a comprehensive study on factors affecting cycle-accuracy, including:branch misprediction, shared data access order, interrupt/exception handling, and shared page access order. Based on the study, we propose a loosely-coupled functional-driven full-system simulator for multicore, namely Transformer. To ensure extensibility and cycle-accuracy, Transformer leverages an architecture-independent interface between FM and TM and uses a lightweight scheme to detect and recover execution divergence between FM and TM.Moreover, the loosely-coupled design also removes the complex interaction between FM and TM and opens the opportunity to parallelize FM and TM to improve performance. Experimental results show that under the same guarantee on cycle-accuracy, Transformer achieves an average speedup of8.4%over GEMS. A further parallelization between FM and TM leads to35.3%speedup. To demonstrate the extensibility and high productivity of Transformer, we extend a functional model QEMU into our framework to construct an X86simulator. The whole extension work is done by a master student only in two months.