Parameter Calculation Model And Interference Analysis Of On-chip Multi-layer Inductors

Recently, numerous results of on-chip inductors have been reported，as a novelinductor structure，On-chip multi-layer inductor has a positive role in the realization oflow power consumption and small–area of chip. However, the study of on-chipmulti-layer inductance parameters and the analysis of interference is insufficient.In order to solve the problem mentioned above, in this thesis, we propose anaccurate physics-based method for calculating dc inductance parameter of on-chipmulti-layer inductors. All inductor size parameters are considered in the methodincluding metal thickness and inter-layer space. We use this method to calculate theinductance of a complete set of inductors with different size parameters and thecoupling coefficient between them (calculated value). In addition，we get their EMsimulation results by using ADS mo mentum (simulated value). The accuracy of themethod is evaluated by comparing the calculated value with the simulated one. It’sshown that the error between calculated values and simulation values of inductance istypically within around3%, and the error between calculated values and simulationvalues of coupling coefficient is typically within around2%. So it can be proved thatthe physics-based method proposed in this thesis has a high accuracy and can be usedfor analyze and design of on-chip multi-layer inductor.According to the method described above, we can use Matlab to build functions tocalculate dc inductance parameter of multi-layers inductor quickly. As the couplingcoeffic ient between the two inductors can effectively reflect the crosstalk betweenthem，we can use the coupling coefficient to analyze the crosstalk between them andrecommend the measures to reduce the crosstalk between inductors.