Research On Synchronization Techniques In Air Craft Video Communication System

Air craft wireless communication technique is an important part of wirelesscommunication technique. Air craft video communication is a branch of air craft wirelesscommunication based on the demand of security supervision, searching and rescue service.Compared with traditional wireless communication, air craft video communication hasfeatures such as high bandwidth and remarkable channel dynamic characteristics, which willbring a high standard to the baseband processing algorithms and system implementation.In this paper, we research on timing synchronization and carrier frequencysynchronization techniques in receivers of air craft video communication system, andimplement the synchronization system with FPGA.In the research on timing synchronization, based on the study of timing synchronizationloop and simulation scheme, we propose a time sequence flow simulation scheme that canadd in and recover constant fractional timing frequency error and mixed timing frequencyerror, with extreme limited cost and high speed. Based on present PN sequence correlationtiming error detection algorithm, we propose an improvement, which reduces the systemcomplexity. At the same time, based on the research on Gardner algorithm, we propose aloop lock detection method which is efficient at loop lock status detection and judgment. Bytime sequence flow simulation with Matlab Simulink, we compare the performance of bothalgorithms, and decide the algorithm and structure of the timing synchronization used in thesystem. And we prove the function of the scheme by Matlab Simulink simulation.In the research on carrier frequency synchronization, for reference, we use the coarseestimation and fine estimation algorithms in carrier frequency recovery scheme based onnon-repeated PN sequence correlation for reference. And we combine the algorithms into a scheme applicable to our project, and give the performance of the algorithm by Matlabsimulation.At the end of this paper, after the fix point process of timing and carrier frequencysynchronization, the top level structure and sub-modules of the algorithms are hardwareprogrammed, verified on the FPGA chip, and integrated into the transceiver system.