Research And Implementation Of Prower Amplifier For Wireless Communication Network

With the development of information technology, the traditional communication networks have become unable to meet the needs of daily life. The consequent wireless communication technology is gradually been widely used in schools, families, public places and many other occasions with its advantages of low cost, low power consumption and mobility. So that people can access to the internet and share the resources anywhere at anytime. With the enhancement of the capacity and transmission rate, the system has put forward higher requirements on the RF chip performance.The power amplifier is critical section in the wireless transmitter, and is also the most power consumption section, its linearity and efficiency performance directly affect the whole transmitter. How to integrate the RF power amplifiers and other RF front-end system on same chip, to achieve more stable, more reliable signal transmission, has become the hot issues of today’s research. Therefore, the study based on CMOS technology high-linearity RF power amplifier has a very important significance, especially the power amplifier applied in wireless LAN system.In this thesis, a brief introduction of some background information is presented, including the development of the wireless Local Area Network, its transmission standards and basic framework of the transmitter, as well as the research level on the power amplifier. Subsequently, analyzes the performance and linearization techniques of the RF power amplifier, then implement a monolithic linear power amplifier by65nanometer process for OFDM-based802.11a/g WLAN operation, include overall circuit design, layout, simulation and measurement results. Compared with other power amplifiers, the Gm-linearization technology and on-chip series-combining transformer(SCT) structure are adopted here to improve the linearity as well as the output power. The follow-up work will be focused on how to decrease the losses, thereby increasing the efficiency of the whole system.This chip is fabricated by TSMC65-nanometer CMOS process and adopted COB package, occupying the total die area of lmm X0.7mm (including electrostatic protection circuit and pads). The power amplifier uses a3.3V DC supply voltage, and consumes200mA quiescent current.