Design Of Template-Based Image Matching ASIC

As one of the most basic digital image processing methods, image matching is usuallyused in motion estimation, automatic target recognition (ATR), etc.. Image matching isalways desired in high accuracy, and also real-time performance. In the ATR systems,image matching is time-consuming task, especially when the template is large or multipletemplates have to be correlated, considering this particularly problem, this paper designedan ASIC based on NCC algorithm aiming at hardware acceleration, meeting the real-timerequirement. When the template is little, two new area-efficient2-D convolvers wereproposed on the basis of various published architectures.The analysis of previous architectures indicated that they all consumes too muchon-chip resources, to avoid these shortcomings, this paper proposed a new designedmultiple template-based image matching ASIC based on NCC algorithm, and its front-endsilicon realization such as architectures definition, RTL coding, verification, synthesis,STA, DFT were also introduced in detail. Two strategies were used to realize thearchitecture:1) multiple SPRAMs interleave store image and on-chip ping-pong operation;2) DA algorithm were used to implement PE array; then as much as8large binarytemplates could be configured into four operation modes of eight1-bit, four2-bit, two4-bitand one8-bit templates using partial product scheme and they could be processed inparallel. In the paper, circuits of kernel sub-modules in ASIC were described in detail, alsothe typical application situation including cascading method. ASIC could support up tomost8ways of160×120template matching against511×511image. The prototype of thechip was emulated on FPGA and also synthesized with Design Compiler, die area was3.2×4mm~2and power consumption was158mW when operate at the highest frequency110MHz. It takes13.23ms to execute120×160template matching with256×320image, therefore is suitable for real-time ATR applications.Considering the little template situation, this paper designed VLSI architectures basedon CC algorithm, which is the common used2-D convolvers. Using partial2-D data reusescheme and Zigzag scan format, two new2-D convolvers were proposed and implementedon FPGA. The I-type features little external bandwidth, the II-type realizes the largestthroughput rate while its external bandwidth is not remarkably increased. Through theperformance evaluation metric, the two convolvers both consume less hardware resourcescompared with previous designs, also external bandwidth and throughput rate could beadjusted by changing design parameter W which gives flexibility to system design and gaina good trade-off between external bandwidth, throughput rate and hardware resource at thesame time. Cascading multiple elementary convolvers could be used to processing arbitrary template size and the paper proposed the method. Compared with common softwareimplementation, the proposed designs gain a high speed-up rate focus on real-timeperformance, so, the two convolvers are suitable for low-cost real-time image processingsystems.