The Train Control And Monitoring System Hardware Platform Designing Based On VME Bus

Train Control and Monitoring System that TCMS, TCMS as a hubfor train module, integrated monitoring and control system in one, responsible forprocessing and distribution of various internal and external data in the running of the train.System requires a large number of communication interfaces to complete the dataexchanging with each module; and as a function system, system needs multiple interfaceboard complete the whole function, and the bus between the board also needs to completethe communication bus data transfer within the system. VME BUS being chosen is a kindof asynchronous parallel bus which developed in eighties of the twentieth century. Up tonow, it has strength in stability, muti-master, interrupt handling, etc for years ofdeveloping and optimization and has special position in system of industrial control.This paper will introduce the hardware design of a kind of industrial control systemwhich is based on VME bus system, it has several parts: VME bus system which achievesin FPGA, after introduce the driver requirements which elaborated in protocol and thesignal planning of the VME master system and VME slave system, we choose the properdrivers and receivers to meet every requirement. The design of the commoncommunication interface which based on ARM, introduce the feathers of the ARM, theminimum system which meet the requirement of the system VxWorks runs. And alsointroduces the feather and designs of additional memories (NAND FLASH and FRAM)and communication interface (USB, RS422, CAN, Ethernet). Next introduce the twospecial communication interface (ETH and HDLC), first introduces the structure ofETH, the main feathers of the choosing Ethernet PHY Transceiver, the design of thepower amplifier and the calculate of the attenuation loop, last estimate the power and thesurface temperature of the AMP chip. The design of HDLC model which controls thespecial devices introduces the structure and the realization of the model. The last part ofthe paper shows the final test results and get the weak point of the system design in actualenvironment, and get an improvement plan to optimize the system design.