SHA-1Algorithms Apply In High-bandwidth Digital Content Protection Repeater

With the rapid development of science and technology, human has enteredInformation Age. As more and more information will be received in our daily life,the security and reliability of information is becoming increasingly important. Indigital audio and video data transmissing, the authorized identification deal HDPChas provided us a new technology to protect intellectual property in order to ensurethe transfer of information is safe, effective and complete.HDCP system allows link no more than seven levels repeater and less than127downstream devices. HDCP repeater need to deal with a lot of data, especially thefirst level repeater needs to collect all downstream devices’ authenticationinformation. SHA-1algorithm was introduced into HDCP repeater to solve theproblem. SHA-1algorithm process generate a160bits message digest from theinformation that length less than264bits. The verified data was compacted in theprocess of authentication using SHA-1Algorithm that decreased the failedprobability of data transformation and increase the speed of the verification.In this paper, the HDCP authentication protocol that including threeverification processing is first analyzesd. Study the mechanism of the HDCPrepeater and discuss the SHA-1algorithm how to apply in the HDCP repeater. Thenaccording to the SHA-1algorithm principle propose three improved structure toimprove the processing speed and increase its throughput. Finally discuss thedesign of the hardware circuit of the SHA-1algorithm.Using top-down design solution and adopt the cyclic structure implement theSHA-1circuit. In the structure, consecutive rounds iteration operation will bemerged into one, so that the original80iteration operation will reduced to40roundcan be done to greatly improve the processing speed of the circuit. Optimize thecritical path when using fast binary adder, based on similar characteristics of thelogic function that adopt the reuse design. The original circuit need four levelslogic reduced to one level that greatly saving resources and reduce the chip area.This paper has strong theoretical and practical significance.