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Algorithm Research And Hardware Implementation Of Video Image2D To3D

Posted on:2013-11-27Degree:MasterType:Thesis
Country:ChinaCandidate:X P ZhaoFull Text:PDF
GTID:2248330377452365Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
3D displaying technology has gradually caused people’s attention with thedevelopment of science. In this paper, it first introduces the technical background of2D to3D and the3D picture of human eye imaging principle,after that an improvedalgorithm of two-dimensional video sequences to extract the depth map and3Drendered images is explained. At the end of the paper, the hardware architecture andimplementation of2D to3D is introduced.The focus and difficult point of this paper is the design and implementation oftwo-dimensional video sequence to depth map generation algorithm and hardwarearchitecture based on the limited hardware logic resources. The main innovativefeatures include:Depth map of the two-dimensional video sequence to generate: appropriate downsampling scale processing of the source image, effectively reducing the amount ofcomputation of the depth map generation process and improving the work efficiencyof the algorithm model; The scene correlation detection, the scene richness detectionand the scene coherence detection provide a reliable basis for the optimization of thedepth map; the accumulated value of the motion vectors provide the most originaldepth, getting the depth image prototype; smooth filter basing on scene correlation isapplied to depth map. In the process we used iteration, in order to avoid a lot of timeand logic resources expenditure in hardware iteration. We have adopted a phasediterative processing, which is in the high-resolution depth of the image processingstage taking low number of iterations, in the low-resolution depth image processingstage taking the high number of iterations. Different stages of processing to quantifythe different number of iterations. The edge contour edge sharpening of depth mapeffectively avoids the blurring caused by moving objects due to pixel gray valuegradient changes slowly shortcomings at the junction of the edge between the movingobject and background. Based on the scene coherence degree and scene richness degree to improve the contrast degree of the depth map, the operator makes movingobjects more clearly evident in the current depth map, the background information ismore uniform and thereby generate stronger level sense of the whole image. Depthmap generation process in this paper is the real-time processing by video sequencesfully automatic, it does not require manual intervention and not need to provide acritical frame of the depth of information, this way make this algorithm extremeflexible and implemented feasibility by hardware.Hardware architecture based on the limited hardware logic resources: hardwarearchitecture is the transition and bridge between the algorithm and chip, or FPGA.The difficulty of the hardware architecture is how to translate the software algorithmsystem without losing to the hardware implementation of frame system, in thisprocess it should also consider the hardware logic resource constraints, the systemclock constraints, and so on. In view of this, in the process of realizing the hardwarearchitecture, the local details is further optimized, including: the down samplingprocess of re-use ram memory space, reducing the hardware logic resources. Hardsmooth filter processing in different resolution stages of the depth map, we can bothinherit the advantages of the improved algorithm and greatly improve the processingspeed of the hardware. In the contrast enhancing of depth map, vertical and horizontalfilter are working simultaneously, in this way it can avoid to open up a large capacitybuffer for storaging data and it also can save the hardware logic resources.This thesis has finished the work to improve the algorithms of2D to3D andimplement by hardware language, laying a certain foundation for my further researchin this area.
Keywords/Search Tags:2D to3D, depth map, contrast enhancing, architecture of hardware
PDF Full Text Request
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