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Otns Decoding Module Of Network Chip Design

Posted on:2013-08-16Degree:MasterType:Thesis
Country:ChinaCandidate:X L WuFull Text:PDF
GTID:2248330374985982Subject:Communication and Information System
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With the rapid development of Internet and the sharp increase of data services,Optical Transport Network (OTN) develops toward the trend of ultra-high-speed, largecapacity and long distance. The application of parallel bus in OTN network is limitedbecause of some defects, such as data alignment, signal delay and crosstalk and so on.Therefore, Serial communication technology, SerDes, which was mainly used in opticalfiber communication before, has been widely used in OTN network. But signal integrityproblems also exist in SerDes technology, so the reliability of data which be sent to theother side through SerDes can not be effectively guaranteed.This paper mainly focuses on the design and verification of the encoding anddecoding circuit modules in the OTN network chip. Aim at the problem of high-speedand large-capacity of data transmission on the OTN network, as well as the problem ofdata reliability caused from employing the high-speed interface SerDes, starting fromthe OTN network’s physical layer coding, an encoding and decoding circuit for an OTNnetwork chip is designed and verified in this paper.Firstly, the paper briefly describes the low-overhead coding techniques, whichmakes introduction and comparison of the8B/10B code with the64B/66B coderespectively. And the theoretical basis of FEC is also described in this paper. Thedetailed introduction of the block diagram of the OTN transmission network, whichindicates the encoding and decoding circuits’ application in OTN network, is alsopresented in this paper.Secondly, this paper describes the overall function of encoding and decodingcircuit of the64B/66B and FEC respectively, and the implementation of encoding anddecoding circuit of each module is also presented in this paper.Finally, this paper builds a VMM-architecture-based verification environment withSystemVerilog and describes the detailed verification strategies for the encoding anddecoding circuit designed in last two chapters. Taking the cell type sent by the OTNnetwork for example, this paper describes the collection of functional coverage andpresents its result. The verification result is shown that the64B/66B encoding introduced only3.125%coding overhead, which makes it suitable for high-capacitycharacteristics of the OTN network. And the encoding delay and decoding delay ofFEC are reduced to14.9ns and155.7ns respectively, making FEC applicable tohigh-speed characteristics of the OTN network. And the burst correcting capability ofFEC is up to11bit, which guarantees the long-distance transmission of data in theOTN network.
Keywords/Search Tags:OTN network, 64B/66B encoder&decoder, FEC encoder&decoder, VMMarchitecture
PDF Full Text Request
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