Radar Active Deception Jamming And The Fpga Implementation

Radar deception jammer interferes target detection or information acquistion on information level through amplitude, time and frequency modulating the interception or regeneration radar signals. And it plays a pivotal role in morden battlefield. However, with the limit of internal resources and processing speed of Field Programmable Gate Array(FPGA), it poses a challenge to FPGA to process these high-capacity and high data rate data which are sampled by high-speed rate Analog to Digital Converter(ADC) in elaborate and broad bandwidth electromagnetic environment and realize active deception jamming efficiently.Based on the problem of radar active deception jamming realization,the dissertation mainly focuses on the following aspects:1. In dissertation, theoretical basis and production mechanism of four kinds active deception jamming such as range-gate pull-off jamming (RGPO), velocity-gate pull-off jamming (VGPO), range and velocity simultaneous pull-off jamming and dense false-target jamming are discussed. Jamming effects and feasibility are verified by MATLAB simulations.2. Based on internal resources of FPGA, data rate recovery, anti-aliasing filtering and DUC modules are designed to solve reality problems encountered and guarantee the quality of jamming signals.3. On the platform of a certain type of broadband radar, four kinds active deception jamming mentioned above are realized based on FPGA. Realization structure and procedure are analyzed in detail4. The debugging of the active deception jamming system is completed, which proves the correctness and reliability of system and design.