45 Nm Light Rigid Defects On Silicon Wafer Imaging Study

Couple with ASML 1900i immersion scanner introduces into photo process; semiconductor has push into 45nm and 32nm. In the 45nm and beyond nodes, immersion photo technology is most important factor and makes the design size fall into a new generation. The key design size decrease, the resolution will improve technology of OPC, PSM and polarization effect will be use frequently. In advance IC process, the chip pattern size wills smaller than one third of exposure waives length, photo mask is key optical character of IC production.Some defects will not influence wafer yield in 90nm or 65nm, but would be the killer in 45 or sub node. This defect will be exposure on wafer, and the yield will lose. This face is a serious challenge in 45nm production.This thesis is focus on critical layers including AA, GT, MET, CH, VIA, and by the method of design different type mask defect which is regular increase of CD. The real mask will be exposure and manufacture and final exposure on wafer FAB. The linearly defect CD on wafer will be measured and use for investigate the influence of etch defect. Beside above work, the test will check the inspection machine catch capability of mask defect, and get the spec line of etch defect type. The last step is compare with wafer exposure data to improve real inspection machine’s catch rate. In this paper, real wafer exposure was checked, and mask inspection exposure simulation software was developed too. The simulation data and real wafer exposure data will be compared.