Study On Preparation And Validation Of Nanometer-Scale OPC

As a critical method of pattern transferring for Very Large Scale Integrated Circuits (VLSI) manufactoring, Photo-lithography has become more and more significant. Especially while indus-try entering the nanometer-scale fabrication era, currently on 65nm and 45nm technology nodes, there are extreme distortions owning to reaching the limit of optical imaging system that cause Res-olution Enhancement Technology and Design For Manufacturability to be inevitable and essential. Optical Proximity Correction (OPC) is a regular Resolution Enhancement Technology (RET). On one hand, Sub-Resolution Assist Features (SRAF), as one of the preparation stage for OPC, inserts assist features around main features so as to enhance contrast of imaging intensity and to improve depth of focus. On the other hand, Hotspot Detection, a basic step of Post-OPC validation, can quickly and credibly locate the error areas under lithography process, therefore OPC recipe tuning or fixing can be aided by it.This dissertation studies and proposes a method using test pattern optimizing SRAF recipe. ID parameters and 2D parameters of SRAF recipe are optimized step-by-step. Comparing with the conventional SRAF recipe method, it can deliver less Edge Placement Error (EPE), wider process window, and simpler recipe content. On the 65 nm technology node experiment, EPE has been decreased 10% with this method. At the same time, the process windows have also improved without SRAF printing-out.This dissertation also implements a hotspot detection method using Support Vector Machine (SVM) and dissection information. It includes spot feature extraction when running OPC dis-section. After the SVM data-training, the Post-OPC hotspots on reticle can be predicted without defining any types of hotspot. On the 45nm technology node experiment, the hotspot detection accuracy is 80%.