Implementations Of OFDM Synchronization System Based On FPGA

Field programmable Gate Array (FPGA) not only has a mature structure, abundantlogic elements, but also is highly integrated and can be configured according to differentapplications, so it is usually used in algorithm implementations and design verifications.Orthogonal frequency division multiplexing (OFDM) has evolved over the years tobecome one of the most important techniques in mobile communications. It caneffectively restrain Inter-Symbol Interference (ISI) and frequency selective multipathinterference in the wireless channel. So it will become the next major communicationsstandards. One of the key technologies of the communications field is thesynchronization technology, it is also the communication must be to overcome thedifficulties one. Compared with the single carrier communication, the synchronizationof the OFDM communication not only needs a highly precise synchronization, but alsoneed a new synchronization method. So, Researching on FPGA OFDM synchronizationsystem has important practical significance.This paper is divided into the following several parts.1) Provided an overview of the basic characteristics of the wireless mobile channeland wireless channel fading.2) Introduced the basic concepts of OFDM technology and give the all-digitalOFDM IF communication system model.3) Analysed the effects of synchronization error to the all-digital OFDM IFcommunication system.4) Researched the principles of the symbol timing synchronization, carrierfractional frequency offset synchronization, symbol timing offset estimation and carrierphase error estimation algorithms.5) On the basis of theoretical studies, I acquire the implementation schemes of theQPSK modulation/demodulation module, the IFFT/FFT module, the Inserting cyclicprefix module, the DUC/DDC module, the symbol timing synchronization and fractionalcarrier frequency offset estimation module, the symbol timing offset and phase error estimationmodule in the all-digital OFDM IF communication system by FPGA. According to theseimplementation schemes, we execute all of these algorithms by coding in VHDL orusing IP Cores supplied by Altera on Quartus II9.0software platform.6) According to the different FPGA hardware circuits, we do post P&R simulations by using Quartus II9.0time analysis tool, then analyze the simulation results and verifythe capabilities of the transfer and synchronization.