A Low-power Serial RS Decoder Design

Reed-Solomon (RS) codes are widely used in digital communication and storage systems due to their ability to correct random and burst errors. The decoding algorithm of RS codes can be divided into hard-decision decoding (HDD) and algebraic soft-decision decoding (ASD), compared with the HDD algorithm, ASD can gain better coding gain, but they are difficult for hardware implementation because of the algorithm complexity, so many efforts are devoted to reducing the complexity of RS ASD algorithm.In this thesis, RS codes and related theories were introduced, including coding theorem, the basic knowledge of Galois field, linear block code, recurrent code, BCH code and RS codes. Compared with other ASD algorithms, the low-complexity chase (LCC) decoding needs less computation complexity with similar or better coding gain. Further efforts have been devoted to reducing the overall complexity of the LCC decoding. A series of transformations are proposed that drastically reduce the area and timing complexity of LCC decoding. In order to achieve higher throughput, the pipelined architecture is often adopted for RS decoders, but their hardware requirements are also high, since there are replicative modules and intermediate results need to be stored between adjacent stages. On the other hand, the power consumption of the pipelined decoder is not preferable. This thesis proposed a novel serial LCC decoder architecture for RS codes. The area requirement of the decoder is reduced greatly by merging the similar modules into one with architecture modifications. In addition, latency is improved through pipelining some computing units and synchronizing adjacent modules. The serial architecture also ensures lower power consumption.The serial LCC decoder has been implemented using Verilog-HDL and verified by Model Sim simulator. It has also been synthesized under Synopsys Design Compiler with SMIC 0.18-um CMOS technology, and can gain a clock frequency of at least 150MHz with the area equivalent to about 27986 NAND2X1 gates. The power of the decoder is 0.0187W through the analysis of Prime-PX.