Study On Novel Efficient Soft-Decision Decoder Of Reed-Solomon Codes

Reed-Solomon(RS) codes are a class of error control codes that find various applications in many fields such as digital communication and storage systems due to their excellent error correction capability. Generally, two kinds of RS decoding algorithms are widely used, namely the hard-decision decoding(HDD) and algebraic soft-decision decoding(ASD). ASD can achieve more significant coding gain than the HDD by making use of the reliability information available from the channel. Among the practical ASD algorithms, the LCC has the lowest complexity cost and similar or even higher coding gain. Therefore, numerous researchers have devoted to study on LCC decoding. The LCC decoding is based on the complicated interpolation algorithm in general. Although much work has been done to alleviate the complexity of the interpolation, it is still the speed and complexity bottlenecks of the LCC decoder. Instead of employing complicated interpolation technique, the LCC decoding can be implemented based on the HDD. This method has lower complexity and shorter latency as well as similar decoding performance compared with the interpolationbased LCC decoding. However, the previous decoders are pipelined and may cause a large amount of idle time since the latency of each stage is fixed. Obviously, it can reduce the hardware utilization efficiency.This dissertation proposes a novel serial decoder to reduce the idle time. To increase the speed of decoder and make modules coordinate with each other in the best way, some blocks use multiple parallel architectures. Moreover, a novel block is proposed to realize syndrome calculation, polynomial selection, Chien search and Forney algorithm in different stages through modifying the algorithms and circuit architectures, which can decrease the complexity remarkably. In addition, this dissertation presents a new common subexpression elimination(CSE) algorithm, which can remove redundant computation for variable multipliers and constant multipliers effectively. Thus, the complexity of the proposed decoder can be further reduced.The error correcting performance for different decoding algorithms has been simulated using C code. The proposed LCC decoder has been modeled with Verilog HDL and simulated by Modelsim simulator tool. Moreover, the proposed decoder has been synthesized under Design Compiler and analyzed power consumption by Prime Time PX with SMIC 0.13?m technology. The results show that the area and the power consumption of the proposed decoder are 0.47mm2 and 0.025 W, respectively. The Verilog HDL model has been implemented in FPGA device using ISE tool as well. The analysis results show that the proposed serial LCC decoder achieves higher speed, lower complexity as well as higher efficiency compared with previous designs.