| With the development of semiconductor technology, the scaling of devices’size and supply voltage forces the traditional analog design to face many tough problems, and digital design is going to take place of the roles of its analog counterparts. For power management system, digital control technology has many advantages compared to analog technology, such as programmability, insensitive to process and environment, intelligent control and short time-to-market. Therefore, digital power management is becoming the focus of attention from the academy and industry.In this dissertation, the basic architecture and characteristics of digital controlled DC-DC converter are studied. Limit-cycle oscillations caused by the quantization effect of digital loop are analyzed. And the digital controlled DC-DC converter systems are modeled and simulated. The existing architectures of digital pulse-width modulators (DPWM) are introduced and their advantages and drawbacks are compared with each other. The dissertation proposes a novel delay-lined structure which utilizes the rising and falling delay to achieve the course and fine resolution of DPWM, respectively. Because of delay cells are reused, hardware cost and power dissipation are saved. For delay synchronization design, the dissertation presents two methods including full-digital solution and mixed-signal solution. Some problems have been found in the simulation of the former, so mixed-signal solution is proposed to solve these problems and improve performances of DPWM.In the dissertation, a10-bit DPWM with the proposed architecture is designed and fabricated in SMIC0.13μm1.2V CMOS process. The chip occupies an area of0.15×0.39mm2. Measurement results show that DPWM can cover the duty ratio range from0.14%to97.0%operating at switching frequency of2.14MHz. A minimum time step of460ps is achieved and the power consumption is24μA/MHz. Linearity measurement results show that DNL is2.08LSB and INL is2.66LSB. |
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