Research Of Low Drop-out Voltage Regulator

Power management is a very hot topic nowadays, especially, in portable devices, power management is crucial to the efficiency of the power supply. Low Drop-out (LDO) voltage regulators are indispensable in the power management systems. While providing stable regulated voltage, LDO isolates the core circuits of a chip from the crude power lines through the merit of the power supply ripples rejection. For example, in wireless transceivers systems, the digital parts of the chip may negatively affect the performance of the radio frequency parts due to the clocks punching through the power lines, where frequency pushing causes screw of the output frequency from a voltage controlled oscillator (VCO). It is pivotal to an LDO to reduce the ripples of the power supply by improving the power supply ripple rejection (PSRR), and also a solution to relief the inter-talk of the core circuit modules in a single chip.The main performance parameters are proposed from the system view in this thesis, the basic parameterized loop model of an LDO is analyzed, and issues are introduced. Then the LDO architectures based on different compensation schemes are discussed.Architectures of LDO for high power supply ripple rejection are analyzed. Consequently, a scheme based on operational transconductance amplifier with diode-connected loading (DCL-OTA) with self-biasing is proposed to improve the performance of PSRR. This scheme is deduced to be applicable, and the performance checked under TSMC O.13μm CMOS process. The measured results show that the output regulated voltage of the LDO proposed is1.2V with minimum input voltage of1.313V under70mA maximum loading and93μA ground current, which introduces a power efficiency of80%. The PSRR is-65dB at100Hz and-68dB at10kHz, respectively. The active die area is0.034mm2.