Design Of Navigation Computer Based On FPGA

Gyroscope Free Strapdown Inertial Navigation System (GFSINS) is a kind of Inertial Navigation System, accelerometers are directly installed in the carrier without using gyroscope. So acceleration is the exclusive in formation source, we can get all the navigation parameters by computing. Usually, we can get the angular velocity of the carrier by installing gyroscope. A high performance gyroscope can give a high precision navigation information, but it will cost a lot to buy a high performance gyroscope. When the carrier has a great line acceleration or a great angular velocity, the gyroscope will withstand a very big impact, which is the biggest drawback of gyroscope. Compared with the Platform type Inertial Navigation System The Strapdown Inertial Navigation System is high reliability, longevity, small volume and so on. Compared with Strapdown Inertial Navigation System with gyroscope, GFSINS is low cost, low power, promote reaction, wide dynamic range and so on. With the emergence of submicron technology, FPGA chips have become more and more popular, thus making the system on a programmable chip (SOPC) design the mainstream technique in embedded system design field.Take the features and application requirements of gyroscope free strapdown inertial navigation system with nine accelerometers into consideration, the thesis put forward a hardware design scheme of gyroscope free strapdown inertial navigation computer based on FPGA. The navigation computer system includes data acquisition module and data decoding module two parts. In the data acquisition module, two AD7656 chips will change the analog signals from nine accelerometers into digital signals controlled by STM32. Therefore, the FPGA can get more system resources, and the speed of calculating is faster than before, the performance of the system has improved too. In the data decoding module, the internal hardware logic of FPGA is constructed by SOPC technology. The key algorithm is accomplished by high-performance 32-bit processor NiosⅡ, in which realized the floating point arithmetic. Finally, the principle chart and PCB design is finished, making a test model, laying the foundation for the further research work of GFSINS.