A GALS-based Multi-core Interconnection And Task Scheduling Mechanism Research

Advances in VLSI design techniques and increasing requirements in DSP's performance have made Multi-DSP a reality and a necessary consequence. The complexity of these Multi-DSP and the traditional on-chip bus is not suitable for the Multi-DSP call for review and revision of on-chip communication techniques. Network on Chip(NoC)has been suggested as the communication resource to overcome the on-chip physical interconnect issues of the Multi-DSP. The reason why NoC can improve the design capacity is that it uses such as GALS transmission protocol and IP reuse technology.This paper presents a Multi-DSP based on GALS (Global Asynchronous Local Synchronous). GALS based design guarantees each core could work in different frequency domains according to the task request, thus the chip's total power consumption can be reduced and eliminate the difficulties on the constrains of the global clocks. Intercommunication with DMA channels between each core achieves high efficiency of data transmission with less processor load. A task scheduling mechanism based on the data flow is proposed to manage the tasks on each core which improves the efficiency of the processor and a MP3 decoder program is implemented on this processor to elaborate the task partition and the schedule of tasks.The project builds a performance simulation environment and timing, area analysis platform to complete the back-end design of Quad-DSP. MP3 decoder is used to verify the performance of GALS based interconnection. A task scheduling mechanism based on the data flow accelerates the speed of MP3 decoder.