Design And Implementation For High Performance Soft-Output K-BEST MIMO Detector

The MIMO technology can significantly increase the channel capacity and spectral efficiency of communication systems without sacrificing additional bandwidth, which is widely considered as a key to launch next-generation Gigabit wireless communication systems. The BER performance and complexity of signal detection at the receiver are of great importance for the deployment of MIMO system. Efficient VLSI design and implementation of MIMO detectors with good detection performance and high throughput have posed a challenge as the computation complexity of optimum MIMO detector grows exponentially with both antenna array size and constellation size.This thesis presents the VLSI architecture and implementation for a 4?4 64-QAM soft-output K-Best MIMO detector, taking performance, throughput and area into account. By introducing the MMSE-SQRD pre-processing method and reusing the discarded paths efficiently to calculate and update the soft information, the detection performance is improved a lot. The on-demand expansion scheme is used to design a deeply pipelined architecture, which increases the extension efficiency from 12.5% to 50% and reduces the computation complexity. Furthermore, considering the characteristic of K-Best scheme, two methods -abandoning the discarded paths and performing ZF-augmentation at the last stage, are proposed to simplify the detection at the bottom levels, which can decrease the latency, area and power consumption significantly without performance degradation.Simulation results show that the proposed detector improves the BER performance by 2.3dB at BER=10-3 compared to the conventional soft K-Best scheme with the same pre-processing method and K=8. The detector can achieve a peak throughput of 855Mbps in SMIC 0.13?m CMOS process, while consuming 223K gates and just 301pJ/bit. This work takes an advantage on both BER performance and throughput comparing with other soft K-Best implementations, and achieves the minimum latency of 120 cycles, which shows the potential to support the next-generation Gigabit MIMO detector.