Research And Design For CDR In Ultra High-speed Optical Fiber Communication Systems

With the increasing amount of communication data, the demand of communication systems is ever increasing. Optical fiber communication has become one of the main transmissions for today's high-speed network transmission means because of its high-speed, large capacity and long distance. Clock and data recovery circuits are responsible for fiber communication systems to recovery clock and retime data, which restricts the speed and transmission quality of optical fiber transmission. It has become as research focus and hot spots for scientists and engineers at present.This paper studies clock and data recovery circuits used in high-speed optical fiber communication systems. We designed the circuits by means of"top-down"design flow. First, the different structures of clock and data recovery circuits are summarized and compared,ultimately clock and data recovery circuits choose analog PLL structure; Second, after in-depth study of the various module of clock and data recovery circuits, we do system-level design and simulation based on the nonlinear Alexander phase detector, LC oscillator, a second-order loop filter.Then the recovered data eye diagram is given to verify the correctness of the system; Finally, give the design of unit circuits and simulate them. This study focuses on the circuits design of clock and data recovery circuits and detail in the design process of improvement Alexander phase detector, LC oscillator, output buffer and special structure of sub-circuits used in ultra high-speed systems.And ultimately give the simulation and analyze results.In the previous study, the circuits are verified in SMIC 90nm Mixed Signal LowLeakage & RF 1.2/1.8/3.3V (1P2M ~ 1P9M) process in Matlab, Hspice and SpectreRF. At the case of 10Gbps data which is a length of 27-1 of pseudo-random NRZ data, simulation results show that the cell circuits can reach the system design requirements.The systems can achieve lock, restore the 10Gbps system clock with low jitter 9pspp and retime data.The design meets the established requirements.