Research Of Key Technology Embedded Heterogeneous Multi-Core Java Processor Based On SPARC

With the development of the embedded technology and semiconductor technology, embedded is more and more widely used in mobile devices. Because of its advantages, Java play a more and more important role in the embedded. However, traditional Java programs need the JVM to run, it will run too slowly and will take up additional system resources.But embedded system has limited resources, thus greatly limits the performance of the system. In embedded systems homogeneous multi-core structure can improve performance, but it will greatly increase the system power consumption. Java processors are implemented as hardware Java virtual machine. Therefore, heterogeneous approach can be used.In the general cores integrate special cores dedicated to improve the performance and does not bring too much power consumption.For the research of key technology embedded Java processor for sparc architecture, this paper studies how to design a heterogeneous multi-core architecture, how to achieve efficient communication between JOP and the AHB bus .Based on the analysis of the LEON3 system structure, AMBA bus, JOP and heterogeneous multi-core structure of the program, this paper proposes heterogeneous multi-core architecture.It is based on the integration of the LEON3 JOP core and other equipment, all devices connected through the AMBA bus, in which high-speed devices connected to the AHB bus, low-speed devices connected to the APB bus.JOP does not support the AMBA bus standard, the internal use of the SimpCon bus and the difference between the very large, so this paper designes a JOP-AHB interface, to achieve the communication between the JOP and AHB bus. The JOP-AHB Interface Based on the study of the SimpCon AHB bus and bus signals and timing,this paper introduce the details of the internal structure of the interface design; and designed a finite state machine to control the interface.Finally, based on a simple introduction to the xilinx design process, on this basis, using ModelSim simulation tool on the JOP-AHB interface, to verify the correctness of the interface, and use integrated tools and power simulator xst Xpower of LEON3 monocytes, LEON3 dual-core, LEON + JOP heterogeneous nuclear footprint, timing, power consumption were analyzed. Obtained by comparing LEON3+JOP heterogeneous multi-core with LEON3 dual-core in power consumption and resource utilization, we still have a lot less and the the maximum clock frequency is not reduced.