Design And Implementation Of A High Through-Put Single/Double-Precision Configured Floating-Point Multiply-Accumulator

The advent of multi-media applications, such as three-dimension(3-D) graphics and signal processing, places stronger demands on high performance floating-point unit(FPU), and of all the floating-point(FP) operations, FP addition and multiplication account for over half, implying that designing a high performance floating-point multiply-accumulator (FPMAC) is really necessary. In addition, the architecture implementing a single-precision FPMAC is familiar with that of a double-precision one and thus a lot of function units can be reused. In order to improve the utilization of hardware resource, a high through-put single/double -precision configured FPMAC is designed. This FPMAC can achieve one double-precision operation or two single-precision operations every cycle. In order to achieve a high through-put FPMAC, a deep pipelined architecture of 8 pipeline stages with a single-cycle accumulator is applied, and also many optimized algorithms including Booth encoding(for partial product generation), Wallace tree(for partial product compression), self-alignment(in order to move part of alignment operation out of accumulation), accumulation result in carry-save, overflow prediction, leading-zero anticipation(LZA) and sparse-tree. Moreover, this FPMAC moves the normalization out of the accumulation, so that the normalization pipeline stage is in sleep status during accumulation and is enabled only when the accumulation loop is over. Gating clock is used to control the pipeline stage which only belongs to double mode so as to increase the through-put of this FPMAC in single mode and also to reduce unnecessary dynamic power. Finally, in seven-metal SMIC 65nm CMOS technology with operating condition of 1.08V and 125℃, the physical design result shows that this single/double-precision configured FPMAC achieves 2 GFlops at 500 MHz.