Research And Implementation Of IEEE 1588 High-precision Network Clock Synchronization

Along with the application of network system deeply into all kinds of realm increasingly, the research of high-precision network clock synchronization system has attracted more attention. Among the numerous network clock synchronization protocol, IEEE 1588 protocol has great potential for development thanks to its highest synchronization precision. network clock synchronization system based on the IEEE 1588 will be the research tide in the network clock synchronization field.This thesis chooses Nios processor as the system's microprocessor after a deep study of the various implementation of IEEE 1588 protocol,meanwhile uses National Semiconductor's DP83640 of the United states as the hardware support for IEEE 1588, and finishes the hardware design of the IEEE 1588 high-precise network clock synchronization system.After a deep analysis of DP8360's internal clock, this essay puts forward a precise method of synchronizing the master clock with the accurate absolute time that the GPS receiver provides,this method takes advantage of DP83640's external time stamp function to estimate the error rate between the master clock and the precise absolute time that the GPS receiver exports;this design takes advantage of the defference between the precise absolute time that comes from the GPS's serial port and the current DP83640's internal clock time to estimate the phase error between DP83640's internal clock and the accurate absolute time. On the basis of these two errors,this design takes advantage of the flexible clock adjustment mechanism that DP83640 provides, and adjust the master clock's phase and rate precisely, thus synchronizes the master clock with the precise absolute time that the GPS receiver exports.In order to implement the high precision clock synchronization between the slave clock and the master clock, this essay puts forward a precise method of synchronizing the slave clock with the master clock. This method uses adjoining timestamps of synchronize messages to estimate the rate error between the master clock and the slave clock, and takes advantage of PTP protocol to estimate the network delay and the slave clock's phase error from master clock. On the basis of these two errors, this design takes advantage of the clock adjustment mechanism that DP83640 provides, and adjust the slave clock's phase and rate precisely, thus synchronizes the slave clock with the master clock.After the test of this network clock synchronization system and the master clock synchronizing to GPS receiver,the average rate error of GPS receiver and the network is 81 ns,and the average phase error is 39 ns.After the synchronization of master clock,in the network environment of 10M rate,the average phase error of the master clock is 25 ns;in the network environment of 100M rate, the average phase error is 207 nanoseconds. Two methods of synchronization achieve a high precision of synchronization,and the accuracy is nanosecond.And they lay a good foundation of this field.