Font Size: a A A

Research On DFT Methods For Integrated Processor SOPC System

Posted on:2012-04-13Degree:MasterType:Thesis
Country:ChinaCandidate:Y F ChenFull Text:PDF
GTID:2218330362450333Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
Integrated Processor is a kind of dedicated information processor, which iscombined with sampling, processing, saving and transmitting. It has high reliabilityand stability. The SOPC (System On a Programmable Chip) technology presents thedesign idea of modular and reusable. Both software and hardware of SOPC areprogrammable, which causing it having powerful and flexible design ability.Therefore, with the SOPC technology, users can build a stable, reliable andpowerful Integrated Processor Simulation Platform quickly.Today, SOPC technology become more and more popular in the system design,but few research address on the test problem of SOPC, most of these focus on theapplications which using SOPC technology. SOPC and SoC are similar both indesigning idea and designing method. After studying the DFT (Design for Test)methods of SoC, this thesis proposes a test strategy for SOPC. SOPC's test strategycan be divided into three sections: test wrapper design, test access mechanism andtest schedule.To solve the problem of wrapper scan chains balanced design, this thesisproposes an algorithm based on mean-value allowance. This algorithm try topartition IP's internal scan chains in reasonable way to make the longest wrapperscan chain as short as possible. Experiments on the cores, which come from theITC'02 Test Benchmarks, approve that this algorithm can effectively reduce IP's testtime through wrapper scan chains balanced design.For the test schedule, this thesis proposes an algorithm based on rectanglepacking. This thesis algorithm IP's TAM width to the rectangle's height, and IP's testtime will be taken as the length of that rectangle. So the test schedule problem canbe described as packing a lot rectangles into a height fixed bin, and make the lengthof that bin as short as possible. Experiment on Integrated Processor SOPC Systemindicates that our algorithm making the test time reduced by 9.95%.At last, this thesis implementes SOPC's DFT methods in the IntegratedProcessor Simulation Platform, experiments of fault injecting and detecting showthat our DFT methods can realize SOPC test, detect system's fault and locate thefailed module.
Keywords/Search Tags:Integrated processor, SOPC System, Design for test
PDF Full Text Request
Related items