.3.3 Volts, 80 Megabytes Sampling Frequency And 10-bit Pipeline Architecture Adc Design

The thesis presents the design of a 3.3V 80Ms/s 10-bit pipeline ADC following an analysis on various high speed ADCs.It is a 1.5bit/stage pipeline ADC with 9 stages. Besides, the following technologies are taken:high-speed, high-gain OTA used in S/H, resulting in higher resolution; open-loop sampling in S/H largely reduced the design difficulties of OTA; the dynamic comparators which are lack of kickback noise keep the analog signal from pipeline stage stable during the high frequency sampling rate; the two-phase non-overlapping clock generator is designed to make full use of the holding time.The chip is being manufactured in TSMC 0.13um double-poly six-metal CMOS mixed-signal process. The consumed die area is 1.1*1.7 mm-. The post simulation result shows that the power dissipation is 138mW with 3.3V power supply and SNDR is 59.885dB when sampling 7.47MHz sinusoid input signal at 83.333MHz sampling rate.