Design And Implementation Of SDH-Based Time Synchronous System For Power System

Modern power system has three important elements:voltage, current and phase, which are the measurement of quality of the power system. With the development of information technology and power system, time synchronization becomes more important to the power system.To solve the problem of time synchronous for power system, this paper presents a method about SDH-based time synchronous system for power system. Through Comparisons among methods of time synchronous system, this paper presents a design method including a Time Slot Amend (TSA) algorithm, using the SDH networks as the media and gives an exact hardware design with FPGA and ARM. In the Specific hardware design, FPGA is responsible for the TSA algorithm; ARM configures interface chips and controls the hardware circuit. Through the flexible design of FPGA and ARM, one circuit can achieve the function of master and slave equipments, and the research cost can be greatly reduced. In the TSA algorithm, master and slave devices transmit time information using one bit of E1 time slot of SDH to each other, the slave device calculates the channel delay difference based on delay time transmitted by the master device to amend the exact time of the slave device. Through analysis, the algorithm can get 250ns precision. At last the ideal and true environment experiment demonstrates the validity of the design.