The Research Of High-Frequency Fatigue Test Machine Controller Based On DSP

With the rapid development of microcomputer and electronic technology, many high frequency fatigue testing machine manufacturers have already applied these advanced technologies into the control of testing machines. This thesis, which is based on advanced technologies, proposes that the high speed processing ability of DSP can be used to achieve fast response to testing machine control and relative logic circuit can be realized through CPLD. The employment of CPLD can not only decrease the circuit wafer space, but reduce the error probability caused by circuit wafer chip, and to accomplish the communication between lower machine and upper machine by means of ISA trunk.The development of high frequency fatigue testing machine is discussed and some improvements are suggested in this thesis.With the help of ANSYS, the author builds the finite element model based on the integrated structure of high frequency fatigue testing machine and analyzes harmonic response as well as figures out the effect of model and poise on testing machine resonance frequency.The realization of PID control arithmetic through DSP facilitates control precision and response speed to attain the expected index. In the development of CPLD, the combination of schematic diagram and VHDL realized several circuit functions, namely, latch, counter and coding.On the basis of Resonance Theory, high frequency fatigue testing machine exerts variable load upon models and the frequency of load can be reached at 80—250Hz. The high frequency fatigue testing machine mentioned in this thesis controls electromagnetic resonant mode exciter through the feedback of load sensor.