Advanced Video Decoding Chip Back-end Research And Implementation

The paper presents methodology and flow of advanced video decoder processor physical implementation and verification. This chip includes 1130K gates,33 dual port SRAMs,4 mask ROMs,3 PLLs, an 8bit DAC, and 239 IOs. Frequency is from 180MHz to 220MHz and process is 0.162um of UMC. Because it has DDR, high work frequency, large power consumption, limited power source, and need meet three types of package, physical implementation is difficult.During physical implementation and verification, we discuss how to create 0.18um flow of physical implementation and verification based on encounter of cadence, how to use CTS method to control DDR timing and reduce implementation cycle, how to handle the different of timing analysis between encounter and primetime, how to create high frequency clock tree, how to reduce static and dynamic IR-Drop during physical implementation.