Based On The Universal Jtag Debugger In The Sopc Design And Realization

With the development of our society, embedded system are quietly becoming one of the most important creations in our daily lives, which exists everywhere in multifunctional mobilephone, mp4, portable devices, intelligent home appliances control, intelligent electronic motor control, etc. As its applications increase, embedded system is much more complicated and hard to develop as well as design which requires higher standards. Debugging, first and foremost, is facing the biggest challenge. Bacause of the diversity of embedded processor, the traditional debugging,"emulator+programmer"is getting more and more restricted. On account of the semiconductor design and production improvement, OCD (On Chip Debugging) and SOPC have greatly changed the traditional debugging methods, improved the debugging efficiency, and the resulting known as a "JTAG" (Joint Test Action Group) OCD debug Principle.In this paper, in-depth study of SOPC design principles and JTAG debugging method, a general debugger is produced in the name of improving the debugger's generality: adding a JTAG debug IPCORE for a specific CPU core into a single FPGA chip, using the SOPC's reusability and FPGA's easy to download and update features, implement debugging variety of embedded CPU architectures in a single hardware chip, reflecting the concept of universal. Concrete production of the system is made up of the ALTERA company's Cyclone series FPGA chip, Quartus II development environment and the Nios II IDE development kit. Research is based on the ARM7TDMI processor JTAG IPCORE and successed in the debugger hardware prototype design. The finished debugging system has achieved the basic debugging features of ARM7TDMI. Following are the principles, ideas and process of the system design and production.