Ultra-wideband Communication Systems Tracking Loops And Its Vlsi Implementation

In impulse-radio ultra-wide band (IR-UWB) communications, even a small timing error would lead to a serious degradation in system performance in the multi-path circumstance. To deal with the challenge, a novel hybrid synchronous sampling timing locked loop is proposed in this paper. Timing error detector, the crucial unit of TLL, is realized based on a maximum-likelihood estimation method. Both mathematical analysis and simulations on S-Curve and timing error variance indicate a high performance of the proposed TLL at low signal to noise rate. It is also demonstrated that in the environment of IEEE 802.15.3a Multi-path channels, the proposed TLL improves system bit error rate (BER) performance by two orders of magnitude when the timing jitters are around half a pulse duration.Furthermore, it is observed through simulations that five figures selective Rake receiver is advisable for a satisfactory system BER performance.Hardware design is accomplished in consider of the tradeoff between tracking performance and implementation complexity. FPGA simulation shows that the proposed TLL is effectively in tracking small timing errors and improve the system BER performance.