System Pulse Ultra-wideband Communication System Timing Synchronization Algorithm And Circuit Structure

Ultra-wideband (UWB) communication, featured by low power, extremely high data rates and ability to co-exist with other services in current spectrum, has been attracting increasing notice in both industry and academia recent years. IR-UWB (Impulse Radio UWB), transmitting sub-nanoseconds pulse sequence in baseband, ensures the system to avoid the performance degradation caused by carrier frequency offset (CFO). Besides, fine multi-path resolution mitigates the energy attenuation resulted from indoor multi-path fading channel and makes it possible to transmit the signals in a rather low power level. Furthermore, calculated by Shannon's Equation, extremely short pulse duration promises high channel capacity, which provides a novel access to the method of high data rate wireless communication.However, these unique features also impose several design challenges, among which low-complexity timing synchronization method is particularly critical. Recent research shows that even trivial timing error may induce large degradation in BER performance.Main work in this dissertation can be concluded as following:1. At algorithm level, CML-based algorithm has been modified by reconfiguring the method of noisy template construction and parameter estimation, by which the normalized mean square error performance has been largely improved.2. At algorithm level, TDT-based algorithm has been modified by reconfiguring the method of dirty template construction. Besides, the estimation equation has also been rectified to further upgrade the feasibility for hardware realization.3. At structural level, an optimized architecture for modified CML-based timing synchronization algorithm, an optimized architecture for modified TDT-based timing synchronization algorithm and an optimized architecture for non-coherent-based CML demodulation algorithm are proposed. From algorithm level to structural level, three algorithms have been completely optimized. Though MALTAB simulation, FPGA verification and Design Compiler evaluation, these optimizations have been demonstrated to fulfill the design objectives of high performance and low complexity.