Des Encryption Circuit

With the development of information technology, the application of computer has come into any field. People can not work, study and live without information technology in the computer era. More and more attention is payed to the security issue in coputer era. According to the Computer Crime & security Survey (2002, Computer Security Institute, USA), data divulgence has already ranked the second infromation safety issue next to computer viruses.DES (Data Encryption Standard) encryption algorithm has stood the long test from when it became the encryption standard to now and has been appiled successfully into more and more fields. It is proved by much practive that it is safe enough for most of the security applications. But as we know, implementing the DES algorithm by software will engross much system resource and make the system function decline. The speed of this implementation can not satisfy some system application also. Furthermore in the actual engineer exercise, in order to achieve a best system performance we should work hard to choose an optimized design according to the system specification. It always confuses us.In this dissertation, the standard DES algorithm is analyzed in detail firstly. Then based on it, the following three implementations of DES encryption/decryption circuits are disscussed and designed.1. Circuit based on conception of time division multiplexing;2. Circuit based on pipeline principle;3. Circuit with pure combinational logic.The three implementations are all simulated and verified with Altera CycloneII^TM FPGA. The verification results of the three circuits are compared with each other. On the whole, the first design has the samllest area, the second is fastest and the third can match some special system requirement which need the valid data output just at the beginning. The verification and the compare can give some guide for engineers to choose an appropriate design in actual engineer application.