Based On The Otn Business Logic In Foga Split System Applications

OTN technology is the compromise production between the electric network and all_optical network,it transplant the Strong and pefect OAM&P idea and function of SDH to the WDM optical network, making up the defect of current WDM system in performance surveillance and maintainance. But as the OTN exchange devices of core OTN technology are not be used all the time. the main reasons are exchange chip's exchange unit can only support ODU1 (2.5G), ODU2 (10G) and advanced operations are still not mature. as the ODU exchange chip's exchange capacitance is not large enough,so how to support the ODU2 (10G) operations transfer on the ODU1(2.5G)'s PCB is key to the logic splitter system.This discourse introduce a way to realize 8 paths OTU1-L or 8 paths [OTU2v-L]/4 to 2 paths OTU2v-L with FPGA, each FPGA will finish 8 paths OTU1-L or 8 paths [OTU2v-L]/4 to 2 paths OTU2v-L's Map/Demap,and implement the master and slave harmless switch, each FPGA do with 2 paths 10G operation.The thesis research the path monitor method in detail. including recovery clock monitor technique,data signal loss monitor technique,frame loss monitor technique,multi_frame loss monitor technique,and also do research to the payload data loss monitor;On the logic splitter,it provides the way of ingress data frame splitter and egress data combination ,makes the OTU2 operation can pass on the OTU1_velocity PCB;in the process of ingress data double transmission and egress data selective receiption,in order to ensure the data transmit stablely when they are switch between master and slave,we have provided a new frame alignment research way,adding the frame alignment before the OTU2 combination,this way comfirm the data switch stably; in the design process of clock reset, providing a global reset and channel reset technique,it is useful for reference in projects design;on the design of high speed interface,adopting the Xilinx'IPcore technique,the thesis do the research and application on the data serial to parallel or parallel to serial conversion and clock recovery technique, ensuring the data can transmit stably during the data transceive. the simulation and system test on board testify the above methods are feasible and effective.