Multi Tap Tdi Visible Light Ccd Imaging System Design And Research

Imaging is one of important applications of the charge coupled device (CCD) as one of the solid state sensors. TDI CCD (Time Delay-integration) is a special linear CCD which works under the time delay and integration mode. The intention of the project is to build a TDI CCD digital still imaging system (abbreviated"TDI CCD system") on the base of the visual high resolution platinum silicon ( PtSi ) TDI CCD sensor which is researched, designed and manufactured at home completely.The traditional method to design the signal processing circuit is mostly built on the DSP (digital Signal Processor) +FPGA (Field Programmable Gate Array) architecture. Although this processing system's speed is relatively higher because of the powerful data processing ability of the DSP, controlling master power must be changed frequently between DSP and FPGA for the time multiplex bus and, consequently, the efficiency of the data transfer of a whole TDI CCD system is low, controlling logical design is complex and much un-convenience is brought to the systematic design and application.The project is intended to build an imaging systematic architecture which is different from the tradition. The framework is based on the embedded soft core NIOS II +FPGA. The advantage of NIOS II as a soft CPU is not only its so high working frequency capability up to hundreds of million hertz as to most of its instructions is completed within one clock period and features 250×100 million instructions per second ,but also its flexibility of reprogrammable. On the other hand, FPGA has the powerful flexibility to match the device and the application within an embedded system perfectly. Meanwhile, FPGA can handle the peak in-out data at lowest cost per channel. So, the architecture proposed for the project serves the purpose of simplification of the systematic design, reduction of the systematic cost and enhancement of systematic reliability.Firstly, the characteristics and working parameters of 4096×96TDI CCD sensor is searched deeply and thoroughly. On this base, the parameters of the objective lens are designed according to the demands and sensor driving circuit on CPLD (Complex Programmable Logic Device) is presented. In order to decrease the noise of the raw signal output from the TDI CCD the CDS (correlated double sample) technology is developed. Simultaneously, 12bit A/D convert is finished. Secondly, the technology of combined multi-channel digital signal into one integrative imagine which meets the demand 20MHz rate of readout of the TDI CCD system is described. Last but not lest, to solve the potential problem of any CCD sensor that is non-uniformity of response to the uniform light, two-point correction method is presented. The principle of the two-point correction is analyzed. As an important part in the dissertation, the implementation methodology of the two-point correction is presented, which is based on the embedded subsystem which contains the soft core NIOS II as CPU and FPGA as hard module.In the last part of the project, a serial of test from device self to the TDI CCD system is implemented as to identify the system's performance. The results of the test show that the design of the purposed TDI CCD system is of reliability and stability with its clear scan imagine and completely satisfy the demand of the project.